Low Power Level Converting Flip-flop Design by Using Conditional Discharge Technique
ثبت نشده
چکیده
Clustered Voltage Scaling (CVS) is an effective way to reduce power consumption in digital integrated circuits. Level-converting flip-flops are the critical elements in the CVS scheme. A single edge implicit pulse-triggered level-converting flip-flop with a conditional clock technique is used in the existing system. It increases the data switching activity due to longer delay. So the power consumption is more. In proposed method LCFF with conditional discharge technique is used. By using this technique the extra switching activity is eliminated by controlling the discharge path when the input is stable high and the total power consumption is reduced and suitable for low power application. The proposed system is scaling in terms of power and delay. The simulations are done by using Mentor graphics tool in 130nm technology.
منابع مشابه
High-performance and Low-power Clock Branch Sharing Pseudo-NMOS Level Converting Flip-flop
Multi-Supply voltage design using Cluster Voltage Scaling (CVS) is an effective way to reduce power consumption without performance degradation. One of the major issues in this method is performance and power overheads due to insertion of Level Converting Flip-Flops (LCFF) at the interface from low-supply to high-supply clusters to simultaneously perform latching and level conversion. In this p...
متن کاملA new low power high reliability flip-flop robust against process variations
Low scaling technology makes a significant reduction in dimension and supply voltage, and lead to new challenges about power consumption such as increasing nodes sensitivity over radiation-induced soft errors in VLSI circuits. In this area, different design methods have been proposed to low power flip-flops and various research studies have been done to reach a suitable hardened flip-flops. In ...
متن کاملLow Power Explicit Pulsed Conditional Discharge Double Edge Triggered Flip-Flop
An explicit pulsed double edge triggered sense amplifier flip-flop for the low power and low delay is presented in this paper. The redundant transitions are eliminated by using the conditional technique named conditional discharge technique. By using the fast improved version of the nickolic latch along with the sense amplifier approach for the latching and the sensing stage the delay factor of...
متن کاملDesigning a Novel Power Efficient D- Flip-Flop using Forced Stack Technique
In Integrated circuits a gargantuan portion of on chip power is expended by clocking systems, which comprises of timing elements such as flip-flops, latches and clock distribution network. These elements absorb approximately 30% to 60% of the total power dissipation in the system. In order to design high performance and power efficient circuits a scrupulous approach should be adopted to reduce ...
متن کاملA Novel Approach for Designing a D-flip Flop Using Mtcmos Technique for Reducing Power Consumption
Power consumption is a major bottleneck of system performance. A large portion of the on chip power is consumed by the clock system. It is made of the any integrated circuit, clock distribution network and flop-flops. A new system will considerably reduce the number of transistor it will lead to the reduction in clocking power and also improve the overall power consumption. Various design techn...
متن کامل